1. Technical Field
The present invention relates to components for generating a signal to drive a step recovery diode (SRD) of a sampler based vector network analyzer (VNA).
2. Related Art
To generate and downconvert high frequency RF signals in a VNA, harmonic samplers are used with higher order harmonics selected for downconversion by an appropriate LO signal when high frequency signals are desired. To generate high frequency LO signals to apply to the harmonic samplers for downconverting the higher order harmonics, a step recovery diode (SRD) is used to generate LO pulses with sufficient power and frequency for the downconversion.
A conventional VNA uses a multiple step downconversion process for high frequencies. A first downconversion is performed with harmonic samplers and a high frequency LO signal. A second downconversion is then performed to further reduce frequency to a baseband using a mixer and a low frequency LO signal.
In such a conventional sampler VNA system with two downconversions, when measurement frequencies drop below the high frequency harmonic sampler LO frequency range, the sampler SRDs are forward biased, effectively disabling the first LO, so that the sampler output is passed directly to the mixers in the second downconversion process. This pass through process is termed a “Direct Mode.” In the direct mode, the mixers in the second downconverter function alone to downconvert the passed through measurement frequency to base band for signal processing. The harmonic samplers and higher frequency LO with all its associated phase locking circuitry is not used in the direct mode. Not only is the first downconversion circuitry not used in direct mode, but also using the direct mode requires the second down conversion to provide the downconversion to base band at higher frequencies. Such a sampler based VNA configuration is described in U.S. Pat. No. 5,524,281 (hereinafter the '281 patent) entitled “Apparatus and Method For Measuring The Phase And Magnitude Of Microwave Signals” and is used in the Wiltron 360 and the Anritsu Lightning line of instruments manufactured by Anritsu Company of Morgan Hill Calif. In particular, see FIG. 2B of the '281 patent with harmonic sampler 174 receiving a LO from harmonic generator 170 providing the first downconversion, and mixer 178 providing a second downconversion with selectable bypasses provided around harmonic samplers 174 for the direct mode. The SRDs 240 for generating the LO in harmonic generator 170 are shown in FIG. 5 of the '281 patent.
FIG. 1 herein illustrates components of a sampler based VNA providing for a first downconversion, a second downconversion and a direct mode as described in the '281 patent. In the VNA, an RF signal, FRF, is provided from signal source 2 and split into two signal portions by power splitter 4. The incident signal is provided to a harmonic sampler 10, while the reflected test signal is provided from coupler 6 to harmonic sampler 11. A SRD 8 provides the LO signal, FLO1, to second inputs of harmonic sampler 10 and 11. The SRD 8 is driven by a LO signal from oscillator 14 through a power amplifier 16 and Pulse Forming Network (PFN) 18. The SRD 8 functions by charging up during a first portion of a clock cycle from LO signal oscillator 14, and then discharging to provide a high voltage pulse that drives the harmonic sampler 10 during a second short portion of the clock period. The output of the harmonic samplers 10 and 11 provide an IF signal, FIF1, that includes multiple harmonics of the FRF signal. One of the harmonics, H, is selected depending on the frequency for the IF signal desired and the rest are filtered out by filters 20 and 21. The outputs of filters 20 and 21 are provided through mixers 30 and 31 to provide the second downconversion to a baseband signal for processing. The second LO signal is provided by oscillator 24. Bypass switches 40 and 41 are used to bypass harmonic samplers 10 and 11 if a direct mode is desired.
The design of a sampler based VNA shown in FIG. 1 relies on the under sampling technique to allow high frequency operation. The relationship of the RF, LO and IF frequencies is described as FIF1=ABS(FRF−H*FLO1). In practice the harmonic H selected from the harmonic samplers 10 and 11 used to create the signal FIF1 is kept as low as possible to reduce the noise multiplying effect of the FLO1 signal.
A key to high frequency operation of the harmonic samplers 10 and 11 is the width of the pulse, tsamp, used to turn on the internal sampling diodes of the harmonic samplers 10 and 11. The first null in the frequency response to FRF occurs at 1/tsamp. To maintain a narrow tsamp, and thus limit any null, the SRD 8 is used. The SRD 8 in turn is driven by a high power amplifier 16 followed by the complex PFN 18.
An example of frequencies used in the system of FIG. 1 is shown in FIG. 2 with a test signal FRF from RF source 2 ranging from 25 MHz to 4 GHz. FIG. 2 shows the relationship for various harmonics H from the harmonic sampler. The PFN 18 is optimized at the highest FLO1 frequency. Degradation of the pulse is allowed at FLO1 below the optimized PFN frequency because the harmonic samplers are more efficient at lower harmonic numbers. The FLO1 range is limited to an octave or 2:1 ratio at the lowest frequency, due to the narrow band nature of the PFN. This octave span of FLO1 is pushing the lower limit. As a reference point high end, conventional VNAs can cover a 1.5 to 1 ratio, such as the Wiltron 360 which covers a range from 357 to 536.5 MHz.
It is instructive to understand how the SRD 8 operates and why the PRN 18 has a lower frequency limit. The SRD 8 stores energy in its forward conduction cycle over a period of (t store), that is the minority carrier lifetime. It releases its charge when reverse biased. The SRD 8 acts as a normal diode except for a very short time after the drive polarity is reversed. The SRD 8 will maintain a charge in the forward biased direction when the reverse bias is applied. This short duration causes current to flow in the reverse direction. This time is called the delay time. When all of the carriers have been removed, the current drops abruptly to zero. At the end of this delay when the current goes from 80% to 20%, the pulse is created. The transition time of this pulse is on the order of 60 to 360 pS. The current needed to charge the SRD is on the order of 100 mA for 10 nS. This implies an impedance of 0.7V/100 mA or 7 Ohms. When the SRD is reverse biased the impedance goes to an open circuit. Driving the SRD with longer duration pulses does nothing other than heat up the diode, as all the minority carriers have been filled. This is the primary reason for limiting the lower FLO1 drive frequency to an octave.
The PRN 18 for a harmonic H=1 must operate over a range of 25 to 50 MHz while providing 100 mA for at least half of the LO signal period from oscillator 14. The load it will drive will be 7 Ohms in one polarity and open circuit in the other polarity. The PRN 18 must also provide a high impedance to the pulse driving the harmonic samplers 10 and 11 while maintaining a low impedance to the power amplifier 16 driving the SRD 8. These seemingly contradictory requirements are met eloquently with the circuit shown in FIG. 3. For convenience, components carried over from FIG. 1 to FIG. 3 are similarly labeled, as will be components carried over in subsequent figures.
In operation with the circuitry of FIG. 3, the power amplifier 16 presents a low impedance moderate voltage level drive to the PFN 18. The PRN 18 transforms this to an even lower impedance using inductor 42 and capacitor 44 to match the 7 Ohm desired impedance of the SRD 8. The inductor 32 and resistor 34 provide a return path for the DC bias developed by the diode action of conduction to open circuit. The capacitor 40 provides DC blocking to prevent a path for the DC signal developed by power amplifier 16 to return to ground through inductor 32 and resistor 34. The inductance 36 between the PFN 18 and the SRD 8 provides for isolation of the PFN 18 from the pulse generated by the SRD 8. The isolation provided by inductor 36 allows the pulse from SRD 8 to have substantially all its energy applied to the harmonic samplers 10 and 11 through the capacitor 38. This capacitor 38 is used to allow the pulse from the SRD 8 to pass through to the harmonic samplers while attenuating the pulsed LO signal and providing DC blocking.
An ideal driver for the SRD 8, as opposed to the power amplifier 8 and PRN 18 of FIG. 3, would have a fixed pulse width 100 mA drive with a small inductor at its output to isolate the pulse from dissipating back into the LO pulse source. The pulse would have a constant width independent of the FLO1 drive frequency. While this is ideal, the nature of pulse generators is such that the pulse duration is derived in some analog fashion. The pulse width, thus, invariably has noise associated with it that gets directly translated by H the harmonic number. The noise will cause deviations in the pulse rate of pulses generated by the SRD.
It would be desirable to provide a sampler based VNA that provides limited noise signals to a SRD over a wider frequency band, allowing use of only a single down conversion to eliminate the need for mixers 30 and 31, and LO oscillator 34, as well as switches 40 and 41 used in the direct mode.